1. Field of the Invention
This invention is related to processing systems and more particularly to out-of-order execution processing systems.
2. Description of the Related Art
A typical out-of-order execution processor (e.g., central processing unit, microprocessor, digital signal processor, processor, processor core, or core) includes a limited number of architectural registers, which are used by instructions to store intermediate and final results prior to storing results to memory. The limited number of architectural registers can limit the number of instructions that can be in flight in the out-of-order execution processor since most instructions require at least one architectural register. However, multiple uses of a particular architectural register may represent independent variables. Register renaming techniques take advantage of that independence to allow more instructions to be in flight in a processor and reduce latencies from register dependencies.
The typical out-of-order execution processor includes more physical registers in the physical register file than architectural registers. Renaming of independent uses of a particular architectural register to different physical registers allows multiple variables to exist concurrently in the physical registers and thus, the processor can concurrently issue multiple independent instructions that utilize the same architectural register. The processor reuses physical registers when they no longer comprise part of the current state of the processor. The processor commits a state of a physical register to the architectural state (i.e., written to the architectural registers) when the processor retires the operation corresponding to the physical register.
Typical register renaming techniques assign one or more physical registers to individual architectural registers and track these register assignments. An architectural register mapping data structure (e.g., table, list or other suitable data structure) stores information (e.g., pointers) that identifies which physical registers contain the contents of a particular architectural register for an operation at a particular time. When a physical register remains renamed as an architectural register that is no longer being used, the number of instructions that are in flight may be unnecessarily reduced. Accordingly, improved techniques for mapping architectural registers to physical registers are desired.